As access times decrease for the high-end semiconductor market, the speed and power specifications are violated for the integrated circuits (ICs) with slower speed grades.
FIG. 1 shows a common complimentary metal oxide semiconductor (CMOS) inverter (also referred to as a buffer) with a p-channel metal oxide semiconductor (PMOS) transistor M1 and n-channel metal oxide semiconductor (NMOS) transistor M2. Typically, the method to reduce propagation delays in this common inverter would be accomplished by increasing the sizing of transistors M1 and M2. This creates a power consumption problem if the device containing a buffer with certain sized transistors is used in a unit or system that requires a device having a slower speed grade.
One way to solve this problem would be by creating the ability to reduce both the operating speed and operating power for the device used in products that are destined for slower applications.
In the present invention, a standard buffer or driver circuit is converted into an adjustable buffer circuit, thereby allowing the speed and power consumption to be reduced.